System Level Costs in SEER-H

The System Level Cost (SLC) feature was first incorporated into SEER-H with release 6.0.  Prior to that release, SEER-H estimated standalone costs of individual work elements plus the costs of creating suitable interfaces between work elements, referring to such mechanical actions as attaching, aligning, calibrating, adjusting, etc., and electronic actions such as energizing, tuning, continuity checking, calibrating, etc.  It did not estimate the sometimes substantial costs of making a group of work elements perform properly as a complete system.  The SLC feature permits more complete estimates to be made ad is a powerful augmentation of SEER-H.   To read this whole paper, click here.

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Embedded Designs Integration Cost Challenges

Embedded design integration is the integration of all efforts (hardware, software, etc.) within an system that is typically dedicated to perform one or a few functions. Typically there are real-time computing requirements involved in these types of designs. Integration costs can at times become a considerable portion of the overall cost on a project. The continuous introduction of newer technologies continue to drive up integration efforts.

Use of old factors that estimated Integration Assembly and Test ( IAT) as a function of overall top effort were weak before but now can produce dangerously low estimates. Part of the reason why IAT costs have classically been painful can be attributed to the fact that it is at this stage where the complicate blend of hardware to hardware or hardware to software comes to a point and must all meet specifications at once! What worked in recent simulations or in isolated tests now becomes painfully clear won’t work at a combined level. This invariably leads to the continuous waves of adjustments, partial redesigns, re-architecting, retests in a desperate effort to close in on the minimum requirements.

For estimation purposes, careful consideration has to be given to the work break down structure of the embedded systems being modeled to ensure adequate estimation of integration effort and risk are covered at all levels. For instance, just applying a 10-35% IAT factor at an enclosure level in order to capture integration of all board and SW underneath it might be okay for some simple systems but not newer technologies which bring along extra complexities. An example is where the design involves custom components (ASICs, FPGAs, etc) which in turn have embedded processors within their fabrics. In these System on a Chip (SOC) designs, it make sense to break out the cost of integrating the SW onto the chip itself. At the next level one could add another rollup to cover the integration of SW to the main board running a general purpose processor, etc.

Another example could be designs that involve multiple separate custom chips running on the board since there might be a significant effort to get these chips to work with each other.

In our SEER H hardware model, we break out these sections with a separate roll up to calculate the IAT. At this point, we take care to set the parameters that describe the complexity of the effort and the experience of the folks doing the work. If this type of design is done often, we would create a knowledgebase (default template) to capture and standardize the estimation approach. As can be seen, many designs can involve layers of IAT which in turn can drive up the final overall IAT numbers considerably beyond 35%.

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Modeling Cost Improvement with SEER-H

For many years, analysts have been collecting information on the cost of producing hardware.  Over time, it has been shown that unit costs of a product typically decrease as the total production quantity increases.  The study of this effect has led to numerous models and theories to predict the cost of product over time for a production program.  Often these algorithms fall into a general category of Learning Curve analysis.  Once thought to model the increased learning in the hands-on personnel, Learning Curve analysis is now used to envelope cost improvements due to many facets of a continuing production program.   To read the whole paper, click here.

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Booz Allen Hamilton, the US Navy and SEER-H

Military satellite communication networks continue to evolve with the insertion of new technologies. Improved systems with greater bandwidth are being developed and deployed to meet the heightened demands of national security.

The Challenge

Due to the lack of early technical and programmatic data and specificity, high-level, early-development-cycle cost estimates are difficult to determine and validate.  The Navy asked Booz Allen Hamilton to develop a business case analysis (BCA) of several acquisition options for the Navy’s AEHF Terminal Program.

Our Solution

To mitigate uncertainty, Booz Allen Hamilton used SEER-H and SEER-SEM, a pair of parametric cost estimating models from Galorath that compelled the technical staff to think specifically about the system’s architecture and its technical definition.  “The SEER tools are equally strong at estimating both software and hardware costs. They do a thorough job of enabling the analyst to deconstruct the system into smaller elements,” David Bracamonte, a Booz Allen senior associate says. “I find SEER easy to use and intuitive.”

The Result

Developing and documenting detailed information about both the software and the hardware elements in the SEER models enabled the client to readily assess the program cost estimate and to conduct a sufficiency review.  The client’s independent cost estimate was reconciled to the Program Estimate developed by Booz Allen. After negotiating minor differences, the client approved the program cost estimate. This approval enabled the program to move forward into Phase II and to initiate the competitive bidding process.

“When you use a parametric model like SEER, you reduce uncertainty by deconstructing the project into smaller, well-defined components; the cost estimate of which can be more readily critiqued by the technical and program management staff,” says Bracamonte.

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